1. Which are the two control unit design approaches?
Hardwired and micro programming…….confirm
2. The control signal is used to enable the tri-stable buffers with the MBR.
MBR out…..confirm
3. The control signal to allow the IR read the value from the internal bus. Thus the instruction stored in the MBR is read into the instruction Register (IR).
LIR…..confirm
4. Which of the following control signals is used to copy the contents of in bus on the out bus so it can be loaded into MAR?
C=B…..confirm
5. Which of the following control signals is used to contents of the memory buffer register are read out onto the out bus by means of applying this signal as it enables the read for the MBR.
MBRout…..confirm
6. Which of the following control signals is used this instruction will enable the write of the instruction register. Hence the instruction that is on the in bus is loaded into this register.
LIR…..confirm
7. is defined as the time required to process a single instruction. Latency……confirm
8. The instruction fetch procedure generally takes time step(s) Three….confirm
9. The syntax of the instruction “branch and link if zero” is
Brlzr ra, rb, rc….confirm
10. The syntax of the instruction “branch if zero(brzr)” is Brzr rb, rc…..confirm
11. Which of the following is responsible for generating signals for external events?
Interrupt generator…..confirm
12. hazard occurs when an instruction attempts to access some data value that has not yet been updated by the previous instruction.
Data……confirm
13. In pipe-line processors, there should be a data path so as not to complicate the flow of instructions and maintain the order of program execution.
Single……confirm
14. In pipe-line processors, there should be a port register file so that if the register write and read stages overlap, they can be performed in parallel.
Three…..confirm
15. Upon receiving the signal the SRC should perform a hard reset.
Strt…..confirm
16. Below given RTL description belongs to which stage of pipe-lining IR2 ? M [PC];
PC2 ? PC+4;
Instruction fetch…..confirm
17. Below given RTL description belongs to which stage of pipe-lining Z4 ? (I-s3: X3+Y3, brl3: X3, Alu3:X3 op Y3,
MD4 ? MD3, IR4 ? IR3;
ALU operation…..confirm
18. Below given RTL description belongs to which stage of pipe-lining Z5 ? (load4: M [Z4], ladr4~branch4~alu4:Z4),
store4: (M [Z4] ? MD4), IR5 ?IR4;
Memory access…..confirm
19. Below given RTL description belongs to which stage of pipe-lining regwrite5: (R[ra] ? Z5);
Write back…..confirm
20. The instruction is completed once memory access has been made and the memory location has been written to
Store……confirm
21. The instruction is completed one the loaded value is transferred back to the register file.
Load……confirm
1. Which of the given RTL description is used to represent store register relative (str) instruction?
(op<4..0>=4):M[rel]<-R[ra]……confirm
2. Which of the given RTL description is used to represent load displacement address (Ia) instruction?
(op<4..0>=5):R[ra]<-disp…….confirm
3. Which of the given RTL description is used to represent load relative address (Iar) instruction?
(op<4..0>=6):R[ra]<-rel……confirm
4. Which of the given RTL description is used to represent conditional branch (br) instruction?
(op<4..0>=8): (cond : PC<- R[rb]),…..confirm
5. Which of the given RTL description is used to represent branch and bank (brl) instruction?
Cond : (PC <- R [rb]))…..confirm
6. Which of the given RTL description is used to represent store register (st) instruction?
(op<4..0>=3):M[disp]<-R[ra]……confirm
7. Which of the given RTL description is used to represent load register relative (Idr) instruction?
(op<4...0>=2) : R[ra] <- M[rel]…..confirm
8. Which of the given RTL description is used to represent load register (Id) instruction?
(op<4..0>=1):R[ra]<-M[disp]……confirm
9. In a simple RISC computer the size of each register is .
32 bits…….confirm
10. A is a device that provides a shared data path to a number of devices that are connected to it.
Bus…….confirm
11. instruction is used to load a register with an immediate data value. Ia……confirm
12. instruction is used to store register contents to memory
St……confirm
13. instruction is used to load register from memory instruction
Id…….confirm
14. Which type of instructions load data from memory into register or store data from register into memory and transfer into memory and transfer data between different kinds of special-purpose registers?
Data transfer……confirm
15. In RTL, which of the following symbols is used to store some data into a register?
:=……confirm
16. A stack based machine is also called .
0-address machine……confirm
17. Which of the following bits of SRC instruction are used to hold the instruction register, used to hold the current instruction
The bits 31 through 0……confirm
18. Which of the following bits of SRC instruction are used to hold program counter(it holds the memory address of next instruction to be executed)?]
The bits 31 through 0……confirm
19. Which of the following bits of SRC instruction are used to hold short displacement or immediate field?
The bits 16 through 0…..confirm
20. Which of the following bits of SRC instruction are used to hold count or modifier field?
The bits 16 through 0…..confirm
21. Which of the following bits of SRC instruction are used to hold an operand, an address index, or a branch target register?
The bits 21 through 17…..confirm
22. Which of the following bits of SRC instruction are used to hold a second operand, conditional test, or a shift count register?
The bits 16 through 12…..... confirm
23. Which of the following bits of SRC instruction are used to hold long displacement field?
The bits 21 thorugh 0…..confirm
24. Which of the following is example of direct indirect addressing mode?
M[[R5] + [R5]]…..confirm
25. Which of the following RTL description is used to represent the target register of Falcon-A instruction
Ra<2..0>:=IR<10..8>…..confirm
26. Which of the following RTL description is used to represent the operation code of Falcon-A instruction
Op<4...0>:= IR<15..11>:……confirm
27. Which of the following RTL description is used to represent the operand or address index of Falcon-A instruction
Rb<2..0>:=IR<7..5>:…..confirm
28. Which of the following RTL description is used to represent the second operand of Falcon-A instruction
Rc<2..0>:=IR<4..2>…..confirm
29. Which of the following RTL description is used to represent the short displacement field of Falcon-A instruction
C1<4..0>:=IR<4..0>……confirm
30. Which of the following RTL description is used to represent the long displacement or the immediate field of Falcon-A instruction
C2<7..0>:=IR<7..0>:…….confirm
31. The instruction Load R1, [R3 + 20] is an example of which of the following addressing modes?
Register
32. In SRC, the op-code for NOP operation is .
0
33. Which of the following RTL description is used to represent all general purpose register of SRC?
R[0..31]<31..0>;...confirm
34. To implement an N-bit barrel shifter in form of a combinational circuit, we require N .
Multiplexers…..confirm
35. A general purpose digital computer has main components 4…..confirm
36. instruction is used to divide a register value by the immediate value in FALCON-E processor
divi…..confirm
37. instruction is used to push the contents of a specified general purpose register to the stack in FALCON-E processor
Push……confirm
38. instruction is used to pop the value that is at the top of the stack in FALCON-E processor
Pop…..confirm
39. instruction is used to load a register with memory contents using displacement addressing mode in FALCON-E processor
Idr…..confirm
40. instruction is used to store a register value into memory using displacement addressing mode in FALCON-E processor
Str…..confirm
41. instruction is used to branch if source operand is less than target address in FALCON-E processor
Bl……confirm
42. instruction is used to branch if source operand is greater than target address in FALCON-E processor
Bg……confirm
43. instruction is used to multiply an immediate value with a value stored in a register in FALCON-E processor
Muli……confirm
44. instruction is used to evaluate logical exclusive or in FALCON-E processor
Xor, xori…..confirm
45. Which of the following measure can be best used for calculating the performance of computation intensive application
MFLOPS……confirm
46. All of the below given processors employ Little-Endian storage format except .
Falcon-A……confirm
47. The instruction shifti R1, R2, 20 is an example of which of the following addressing modes?
Immediate…..confirm
1) The multiplexer----------- is used to decide which value is transferred to be written
back to the register file.
•
MP2
•
MP3
•
MP4
•
MP5
2) Which of the following condition is evaluated when executing the branch
instruction “brzr R2, R1”?
•
If(R2==0)
•
If( R1 >0 )
•
If( R1==0)
• If( R1 <
0)
3) In case of
SRC processor, bits------- of IR (instruction register) are reserved for the opcode.
•
0 to 4
•
11 to 15
•
27 to 31
• 59 to 63
4) Which of the given RTL description is used to represent “load instruction register” (ldr) instruction?
•
(op<4..0>=6): R[ra] rel
•
(op<4..0>=2): R[ra] M [rel]
•
(op<4..0>=2): M[disp] R [ra] CONCEPYUAL
•
(op<4..0>=2): M[rel] R [ra]
5) Instruction is used to divide a register value by immediate
value in FALCON-E
processor.
•
div
•
idiv
•
divi
•
divim
6) Which field of machine
language instruction is the “type
of operation” that is to be performed.
• Op-code(or the operation code)
•
CPU register
• Memory Cells
• I/O Location
7) Which of the following control signal is NOT activated
during instruction fetch operation?
• PCout
•
LC
• LMAR
•
Cout
8) In case of
FALCON-A---------- instruction are present which
are not present
in SRC processor.
•
create and
destroy
•
in and out
• open and close
•
read and write
9) provides
a temporary storage for the address of memory location
to be accessed.
• MAR
•
MBR
•
PC
•
LPC
10) Which of the following register is used to enable the tri-stable buffers with the MBR?
• MBRout
•
MARout
•
LMBR
•
INC4
11) What functionality is performed by the instruction “str R8, 34” of SRC?
• It will load the register R8 with the contents of the memory location M[PC+34]
•
It will load the register
R8 with the contents of the memory location M[34]
• It will store
the register R8 contents
to the memory location M[PC+34]
•
It will store
the register R8 contents
to the memory location M[34]
12) Program Counter(PC) holds the memory address of:
• Previous Instruction
•
Current Instruction
•
Next Instruction
• Previous and Current Instruction
13) What is the working
of Processor Status Word (PSW)?
• To hold the current status of the processor
•
To hold the current address
of the process
•
To hold the instruction that the computer
is currently processing
•
To hold the address of the next instruction in memory that is to be executed
14) mul is the
example of a(n)----------- operation.
• Logic
• Shift
• Arithmetic
•
Data transfer
15) Control Signal
for RTL “IR< ---MBR” will be---------
• MBRout,LIR
•
PC< --C
•
PC< --MBR
• PC< --IR
16) What does the instruction”ldr R3, 58” of SRC do?
• It will load the register R3 with the contents of the memory location M[PC+58]
• It will load the register
R3 with the relative address
itself(PC+58)
•
It will store
register R3 contents
to the memory location
M[PC+58]
•
It will store
the value of register R3 at the relative address
itself(PC+58)
17) The status
register of the 68000 has-------- condition
codes.
•
2
•
3
•
5
•
8
18) Which of the instruction is used to load register
from memory using relative
address?
•
ld instruction
•
ldr instruction
•
lar instruction
•
str instruction
19) For the------ type instruction, we require a register to hold
the data that is to be loaded
from the memory,
or stored back to the memory.
• Jump
•
Control
•
L
• load/store
• Branch
20) In a processor,----------- is responsible for the synchronization of internal as well external
events.
• Memory Unit
•
Data Unit
•
Arithmetic
& Logic Unit
• Control Unit
21) In CPU design,----------- creates or forms the interface between the data path and control unit.
•
Buses
• ALU
•
Control signal
•
cache
22) Control signal
enables the input to the PC for receiving
a value that is
currently on the
internal
processor bus.
•
LPC
•
INC4
•
LC
• Cout
23) In SRC, the effective address is computed a run-time
by adding a constant to value
of-------- register.
•
FLAGS
•
IR
•
PC
•
Ra
24) control signal
allow the content
of the program counter register
to be written onto the internal processor
bus.
• INC4
•
LPC
•
PCout
• LC
25) In---------- instruction format
of EAGLE processor, there is no field reserved
for the operands.
• Type V
•
Type Y
•
Type X
• Type Z
26) In Type C instruction
of SRC,--------- bits are allocated
for constant values.
•
16
•
17
•
21
•
22
27) A general
purpose digital computer
has--------- main components.
•
2
•
3
• 4
•
5
28) The instruction---------- will load the register R3 with the contents
of the memory location M[PC+56].
•
lar R3,M[56]
•
ldr R3,M[56]
•
ldr R3,56
•
lr R3,[56]
29) In FALCON-A
instruction format of Type-2
constants and variable should be in the range
of.
• -132 to +131
•
-164 to + 163
•
-32 to + 31
•
-128 to + 127
30) In a FALCON-A assembly
program, labels are used to implement---------- jump.
• Direct
• Indirect
• Relative
• Displacement
31) In “Jump [8]” instruction, the size of the
constant fields is-------- bits.
• 4
•
5
• 8
•
16
32) The multiplexer--------- is used to decide which
value is transferred to be written
back to the register file.
• MP2
•
MP3
•
MP3
•
MP5
33) is a register which takes input from the ALSU
as memory address
to be accessed and transfer
the
memory contents
on that location onto the memory sub-system.
• PC
•
MBR
•
MAR
•
IR
34) In pipe-lined processor, there should be a-------- port register
file so that if the register write and register
read
stages overlap
they can be performed in parallel.
• Four
•
Three
•
Two
•
One
35) Which of the following registers is used as an implicit
operand in MUL/DIV
instruction of FALCON-A?
•
R0
•
PC
•
IR
•
SP
36) Which one of the following control signals causes the data from
the bus to be read into the register MAR.
•
MARout
• MARin
• LMAR
•
None of the given
37) Which of the following operations is NOT performed by using miscellaneous instruction?
• Clearing all registers
•
Stopping the processor
•
NOP
• Returning from
a procedure
38) To set the value of micro-PC
from branch address,
the value of 4 to 1 multiplexer is------------
• 00
•
01
•
10
•
11
39) The instruction “PUSH A” is an example
of ------------
•
0-address instruction
• 1-address instruction
•
2-address
instruction
•
3-address
instruction
40) Which of the following
branch instruction has a condition
which is always executed?
•
JZ
• JUMP
•
JPL
•
JMI
41) hazard occurs when attempting to access same resource in different ways at the same time.
• Branch
• Data
•
Structural
•
Instruction
42) is an example of Miscellaneous instruction.
•
Shift
•
Store
•
Halt
• Call
43) Which type of instructions enables mathematical computations?
• Arithmetic
•
Control
• Data transfer
•
Numeric
44) VLIW
Stands for-------------
• Variable Length Instruction Word
• Very Long Instruction Word
•
Very Long Instruction Width
•
Variable Length Instruction Width
45) Which of the following is NOT related
to the architecture of the computer?
• Instruction set
•
Control signal
•
I/O mechanism
•
Memory addressing modules
46) In SRC, the general-purpose register file includes------------- registers,
each 32 bit wide.
• 6 Registers R0 to R15
•
24 Registers R0 to R23
•
32 Registers R0 to R31
•
64 Registers R0 to R63
47) Which of the following RTL description is used for specifying the operation of an SRC instruction?
•
IR<31..27>
•
IR<22..26>
•
IR<21..17>
• IR<21..0>
48) What is the size of the memory space
that is available
to FALCON-A processor?
• 2^8 bytes
•
2^16 bytes
•
2^32 bytes
•
2^64 bytes
49) How can we refer to
an instruction register (IR), of 16 bits (numbered 0 to 15) using RTL.
• IR<16..0>
•
IR<15..0>
•
IR<16..1>
•
IR<15..1>
50) What is the working
of Processor Status Word (PSW
• To hold the current status of the processor.
• To hold the address
of the current process
• To hold the instruction that the computer
is currently processing
•
To hold the address of the
next instruction in memory that is to be executed 51) What does the instruction “ldr R3, 58” of
SRC do?
•
It will load the register R3 with the contents of the memory
location M [PC+58]
• It will load the register R3 with the relative address
itself (PC+58).
• It will store the register R3 contents
to the memory location M [PC+58]
• No operation
52) What is the instruction length of the FALCON-E processor?
• 8 bits
•
16 bits
•
32 bits
• 64 bits
53) Which one of the following portions
of an instruction represents
the operation to be performed?
• Address
•
Instruction
code
• Opcode
•
Operand
54) Which one of the following
is the highest level of abstraction in digital design
in which the computer architect views the system for the description of system components and their interconnections?
• Processor-Memory-Switch level (PMS level)
•
Instruction
Set Level
•
Register Transfer Level
• None of the
given
55) Identify the opcode,
destination register (DR), source registers (SA and SB i/e source register
A and source register B) from the following example.
ADD R1, R2, R3
• Opcode= R1, DR=ADD, SA=R2,
SB=R3
•
Opcode= ADD, DR=R1, SA=R2,
SB=R3
•
Opcode= R2, DR=ADD,
SA=R1, SB=R3
•
Opcode= ADD, DR=R3,
SA=R2, SB=R1
56) Which one of the following circuit
design levels is called
the gate level?
•
Logic Design Level
•
Circuit Level
•
Mask Level
•
None of the given
57) The CPU includes three types of instructions, which have
different operands and will need different representations. Which one of the instructions requires two source
registers?
• Jump and branch format
instructions
•
Immediate
format instructions
• Register format instructions
•
All of the above
58) P: R3 <- R5 MAR <- IR These two are instructions
written using RTL .If these two operations is to occur simultaneously then which symbol
will we use to separate
them so that it becomes a
correct statement with the condition that two operations occur simultaneously?
• Parentheses ()
•
Arrow <-
•
Colon :
• Comma ,
59) In which of the following instructions the data move between
a register in the processor
and a memory location (or another register) and are also called data movement?
• Arithmetic/logic
•
Load/store
•
Test/branch
•
None of the given
60) Which one of the following
is the highest level of abstraction in digital design
in which the computer architect views the system
for the description of system
components and their
interconnections?
• Processor-Memory-Switch level (PMS level)
• Instruction Set Level
• Register Transfer
Level
• None of the
given
61) Identify the opcode,
destination register (DR), source registers (SA and SB i/e source register
A and source register B) from the following example.
ADD R1, R2, R3
• Opcode= R1, DR=ADD, SA=R2,
SB=R3
• Opcode= ADD, DR=R1,
SA=R2, SB=R3
• Opcode= R2, DR=ADD, SA=R1,
SB=R3
• Opcode= ADD, DR=R3, SA=R2,
SB=R1
62) Which one of the following circuit
design levels is called
the gate level?
• Logic Design Level
• Circuit Level
• Mask Level
• None of the
given
63) The CPU includes three types of instructions, which have
different operands and will need different representations. Which one
of the instructions requires two source registers?
• Jump and branch format
instructions
• Immediate format
instructions
• Register format instructions
• All of the above
64) P: R3 <- R5 MAR <- IR These two are instructions
written using RTL .If these two operations is to occur simultaneously then which symbol
will we use to separate
them so that it becomes a
correct statement with the condition that two
operations occur simultaneously?
• Parentheses ()
• Arrow <-
• Colon :
• Comma ,
65) In which of the following
instructions the data move between a register in the processor
and a memory location (or another
register) and are also called data movement?
•
Arithmetic/logic
•
Load/store
•
Test/branch
•
None of the given
66) What does the word ‘D’ in the
‘D-flip-Flop’ stands for?
• Data
• Digital
•
Dynamic
• Double
67) The instruction-------------- will load the register R3 with the contents
of the memory location M [PC+56]
• Add R3, 56
• lar R3, 56
• ldr R3, 56
• str R3, 56
68) What is the instruction length of the FALCON-E processor?
• 8 bits
• 16 bits
• 32 bits
69) Which one of the following are the code size and the Number of memory bytes
respectively for a 2-address instruction?
• 4 bytes,
7 bytes
• 7 bytes, 16 bytes
• 10 bytes,
19 bytes
• 13 bytes,
22 bytes
70) Which one of the following portions
of an instruction represents the operation
to be performed?
• Address
• Instruction code
• Opcode
• Operand
71) Which operator
is used to ‘name’ registers, or part of registers, in the Register
Transfer Language?
• :=
•
&
•
%
• ©
72) What is the size of the memory space
that is available to FALCON-A processor?
• 2^8 bytes
• 2^16 bytes
•
2^32 bytes
•
2^64 bytes
73) An “assembler” that runs on one processor and translates an
assembly language program written for another
processor into the machine language of the other processor
is called a ----------------
• compiler
•
cross assembler
•
debugger
•
linker
74)
Which instruction is used to store register
to memory using relative address.
•
ld instruction
•
ldr instruction
•
lar instruction
•
str instruction
75) Which of the following can be defined as an address
of the operand in a computer type instruction or the target address in a branch type instruction?
•
Base address
• Binary address
• Effective address
• All of the given
76) How can we refer to
an instruction register (IR), of 16 bits (numbered 0 to 15) using RTL?
•
IR<16..0>
•
IR<15..0>
•
IR<16..1>
•
IR<15..1>
77) What functionality is performed by the instruction “str R8, 34” of SRC?
• It will load the register
R8 with the contents of the memory
location M [PC+34]
•
It will load the register
R8 with the relative address
itself (PC+34).
•
It will store
the register R8 contents
to the memory location M [PC+34]
•
No operation
78) Which type of instructions help in changing the flow of the
program as and when required?
• Arithmetic
•
Control
• Data transfer
•
Floating point
79) Which of the following statements is/are true about RISC
processors’ claimed advantages over CISC processors? (a) Keeping regularly accessed variables in registers as opposed to keeping them in memory
facilitates faster execution. (b) RISC CPUs outperform CISC CPU’s in
procedural programming environments. (c) Instruction pipelining has helped RISC CPU’s to attain a target of 1 cycle per instruction.
(d) It is easier to maintain
the “family concept” in RISC CPU.
• (a),
(b) &(c)
•
(b), (c)
& (e)
•
(c), (d) & (e)
• (a), (c) & (d)
80) Which one of the following is the highest
level of abstraction in digital design
in which the computer architect views the system
for the description of system
components and their
interconnections?
• Processor-Memory-Switch level (PMS level)
•
Instruction
Set Level
•
Register Transfer Level
•
None of the given
81) Which one of the following is/are
the features of Register
Transfer Language? a) It is a symbolic
language
b) It is describing the internal organization of digital computers
c) It is an elementary operation performed (during
one clock pulse),
on the information stored in one or more registers d) It is high level
language.
▪
(b) only
▪
& (b) only
▪
,(b) &
(d)
▪
(b),(c) &
(d)
81) Motorola MC68000
is an example of-------- microprocessor.
•
CISC
•
RISC
•
SRC
• FALCON
82) Which one of the following registers holds the instruction that is being
executed?
• Accumulator
•
Address Mask
•
Instruction Register
•
Program Counter
83) For any of the instructions that are a part of the instruction set of the SRC, there are certain required; which may be used to select the
appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
• Registers
•
Control signals
•
Memory
•
None of the given
84) The external
interface of FALCON-A consists
of a data bus.
•
8-bit
•
16-bit
•
24-bit
•
32-bit
85) In which one of the following
techniques, the time a processor spends waiting for instructions to be fetched
from memory
is minimize
• Perfecting
•
Pipelining
• Superscalar operation
•
Speedup
86) enable the input
to the PC for receiving a value that is
currently on the internal processor bus.
• LPC
• INC4
• LC
• Cout
87) The processor must have a way of saving information about its state or context so that it can
be restored upon return from the -------------
•
Exception
• Function
•
Thread
•
Stack
88)is the ability of application software
to operate on models of equipment
newer than the model for
which it was originally developed.
• Backward compatibility
•
Data migration
• Reverse engineering
•
Upward compatibility
89) control signal allows the
contents of the Program Counter register to be written onto the internal processor bus.
• INC4
• LPC
• PCout
• LC
90) Which one of the following registers stores a previously
calculated value or a value loaded from the main memory?
• Accumulator
• Address Mask
• Instruction Register
• Program Counter
91) Computer system
performance is usually measured
by the ---------------
• Time to execute a program or program mix
•
The speed with which it executes
programs
•
Processor’s
utilization in solving the problems
•
Instructions that can be carried out simultaneously
92) The external
interface of FALCON-A
consists of a address bus.
• 8-bit
•
16-bit
•
24-bit
•
32-bit
93) Which one of the following register(s) that is/are programmer
invisible and is/are required to hold an operand
or result value while the
bus is busy transmitting some other value?
• Instruction Register
• Memory address
register
• Memory Buffer
Register
• Registers A and C
94) The external
interface of FALCON-A
consists of a address bus and
a data bus.
• 8-bit , 8-bit
•
16-bit , 16-bit
•
16-bit , 24-bit
• 16-bit , 32-bit
95) is the ability of application software
to operate on models of equipment newer than the model for
which it was originally developed.
• Backward compatibility
• Data migration
• Reverse engineering
• Upward compatibility
96) Which one of the following registers stores a previously
calculated value or a value loaded from the main memory?
• Accumulator
• Address Mask
• Instruction Register
• Program Counter
97) Which one of the following register(s) contain(s) the address of the place
the CPU wants to work with in the main memory and is/are
directly connected to the RAM chips on the motherboard?
• Instruction Register
• Memory address register
• Memory Buffer
Register
• Registers
A and C
98) FALCON-A processor
bus has 16 lines or is 16-bits
wide while that of SRC is wide.
• 8-bits
•
16-bits
•
32-bits
•
64-bits
99) enable the input to the PC for receiving
a value that is currently on the internal
processor bus.
• LPC
• INC4
• LC
• Cout
100) The external
interface of FALCON-A
consists of a data bus.
• 8-bit
•
16-bit
• 24-bit
•
32-bit
101) For any of the instructions
that are a part of the instruction set of the SRC, there are
certain
required; which
may be used to select
the appropriate function
for the ALU to be performed, to
select appropriate registers, or the appropriate memory location
• Registers
• Control signals
•
Memory
• None of the
given
102) Among the two approaches available to design a control unit,
hardware approach is relatively----------
as compared
to micro-programming.
•
Slow
•
Fast
•
Average
•
Better
103) The MAR is connected
directly to the-----------
• MBR
•
CPU Internal bus
•
CPU external bus
•
LIC
104) Which of the
following is not a part of processor state?
• IR
•
PC
• Stacks
•
Registers
105) form the branch control
field in the micro instruction.
• C Bits
• M Bits
• B BITS
•
M Bits
106) During the RESET operation of processor, control
step counter is set to---------------
•
1
• 0
•
2
•
-1
107)
An “assembler” that runs on
one processor and translates an assembly language program written for another processor into the machine
language of the other
processor is called a------------
• Compiler
•
Cross assembler
•
Debugger
•
linker
108) In FALCON-A
processor, the size of
each I/O port is---------------
• 16 bits
• 8 bits
•
8 bytes
• 256 bytes
109) is defined
as the number of instructions processed per second.
• Memory access
•
Throughput
•
ALU operation
• Latency
110) In FALCON-A
ISA, which of the following
opcodes is used to perform
“No Operation”?
• 20
•
21
• 22
•
23
111) is an example of Miscellaneous instruction:
• Shift
• Store
•
Halt
•
Cell
112)
To apply two shifts to an
input number using the barrel shifter, the control signals S1 and S0 of the
shifter should be------ --.
• S1 = 1 and S0 = 1
•
S1 =
0 and S0 = 1
•
S1 = 1 and S0 = 0
•
S1 =
2 and S0 = 0
113) Which one of the followings is the correct RTL description for sign extensions of an
8-bit constant:
•
(8aIR<7>©IR<7..0>)
•
(8aIR<5>©IR<8..0>
• (8aIR<7>©IR<6..0>
•
(8aIR<8>©IR<7..0>
114) In MC68000,-------------- register is used as stack pointer:
•
A0
•
A7
•
D0
• D7
115)
In which of the following instructions, the data moves between
a register in the processor and a memory
location:
• Arithmetic
•
Load/ Store
• Branch
• Logic
116)
The size of data
bus of mc68000 processor is:
•
8 bits
•
16 bits
• 20 bits
•
32 bits
117) Which one of the following operations is NOT performed by using miscellaneous instructions?
•
Clearing all registers
•
Stopping the processor
•
NOP
• Returning from a
procedure
118) In case of
FALCON-A------------- instructions
are present which are not present in the SRC processor:
•
Create and destroy
•
In and out
•
Open and close
•
Read and write
119) In Type C
instruction of SRC ,------------------ bits are allocated for content value:
•
16
•
17
•
21
•
22
120) RISC stands
for?
• Registers internal
system cache
• Reduced instruction set computer
• Registers instruction set computer
•
Reduced internal system
computers
121) Which of the followings is not an example of super-scalar processors?
• PowerPC601
•
IAPX88
•
Intel P6
•
DEC Alpha
21164
122) In EAGLE processor, which of the following notations is used to represent a memory word stored at address
8?
•
M [8] <0..15>:= M[8]©M[9]
•
M[8]<15..0>:=M[9] ©M[8]
• M[8]<15..0:=M[8] ©M[9]
•
M[8]<0..15>:=M[9] ©M[8]
123) form the branch address
field in the micro instruction:
• C bits
•
M bits
• B bits
•
A bits
124) What does the
instruction “idr R3, 58”
of SRC do?
• It will load register R3 with the contents of the memory
location M[PC+58]
•
It will load register R3 with the relative address
itself (PC+58)
•
It will store
register R3 contents
to the memory location
M[PC+58]
• It will store the value of register R3 at the relative address
itself (PC+58)
125)
The SPARC architecture defines a-------------------- that allows
for multiple address
spaces.
• Memory Location
Unit(MLU)
• Memory Mapping
Unit( MMU)
• Memory Shifting Unit (MSU)
•
Memory Arithmetic Unit (MAU)
126) For a processor having 32
general purpose register,-------------- bits are required for each register
field in the
instruction:
•
32
•
3
•
8
•
5
127)
Which of the following
registers is/are programmer invisible and is/are required to hold an operand or
result value while the bus
is busy transmitting some other value?
• Instruction register
•
Memory address
register
•
Memory Buffer Register
•
Registers A
and C
128)
In SRC which of the following is a notation which is used to repeat
32- bit memory word stored
at address starting from 56?
• M[56]<31..0>:=M[56]M[57]M[58]M[59]
•
M[56]<0..31>:=M[56]M[57]M[58]M[59]
•
M[56]<0..31>:=M[59]M[58]M[57]M[56]
• M[56]<0..31>:=M[59]M[58]M[57]M[56]
•
129)
Which of the following branch instruction has a condition
which is always executed?
•
JZ
•
JUMP
•
JPL
•
JMI
130)
Which of the following EAGLE instruction is used to initialize all the registers by setting them to 0?
• NOP
•
HALT
•
INIT
•
RESET
131)
Which notation do we use to name different fields of a register in RTL?
• 0
• <=
• +
•
:=
132) Which of the following
instruction is considered most important in pipelined EAGLE architecture?
• HALT
•
NOP
•
INIT
• RESET
132) SPARC uses
a simple set of---------- instruction format.
• 64-bit
•
12-bit
•
16-bit
• 32-bit
•
The ALSU function
“INC2” increments the----------- by 2 and the output is
stored in the buffer
register.PC,A
•
IR,A
•
PC,C
• IR,C
134)
Which temporary register is
loaded with either a register value from the register file or a constant from
the instruction?
• Y3
•
X3
•
Z4
•
Z5
135)
“Finite-state machine”
concepts are usually used to represent the control unit where every state
corresponds to clock cycles(s).
• 1
•
2
•
4
•
16
136) Total number of data registers in Motorola
68000 processor are----------
• 8
•
12
•
24
•
32
137) instruction
is used to load a register with an immediate
value.
• la
•
lar
•
ld
•
ldr
138) A computer
belongs to which of
the following subset
of the systems?
• Mechanical system
• Electrical system
• Optical system
• Magnetic system
139) In FALCON-A
processor , the size
of each I/O port is-------------
• 16 bit
• 8 bit
• 8 bytes
•
256 bytes
140) Type A of SRC has which of the following
instruction?
a)
andi, instruction
b)
No operation or nop instruction
c)
lar instruction
d)
ldr instruction
e)
Stop operation or stop instruction
• (a)&(b)
• (b)&(c)
• (a)&(e)
•
(b)&(e)
141)
In which of the following technique, the time a processor spends waiting for instruction to be fetched
from memory is minimized?
• Perfecting
• Pipelining
•
Super-scalar
operation
•
Speed up
142) is the ability of application software
to operate on models
of equipment near than the model
for which
it originally developed.
• Backward compatibility
• Data migration
• Reverse engineering
• Upward compatibility
143) Which of the following register stores a previously calculated value or a value loaded
from the main memory?
• Accumulator
• Address Mask
• Program counter
144) Computer system
performance is usually measured
by the ----------
• Time to execute
a program or program mix
• The speed in which it executes programs
• Processor’s utilization in solving the problems
• Instructions that can be carried out simultaneously
145) Which of the following code size and the number
of memory bytes respectively for a 2-address instruction.
• 4 bytes, 7
bytes
• 7 bytes ,16 bytes
• 10 bytes , 19 bytes
•
13 bytes, 19 bytes
146)
Which of the the given
below measures is/are
used for comparison of performance of various machine?
•
Execution time
•
MFLOPS
•
MIPS
•
All of the given
147) There are------------ type
of RESET operation
in SRC.
•
Three
•
Four
•
Two
•
five
148) Type checking
allows the------------- to determine memory
for variables.
•
Compiler
•
Debugger
•
Linker
•
loader
149)
In FALCON-A processor, memory word size is----------------
•
1 byte
•
4 bytes
•
8 bytes
•
2 bytes
150)
What functionality is performed by the by the instruction “lar R3, 36” performed.
• It will load the register
R3 with the contents of memory location
M[PC+36]
•
It will load the register
R3 with the relative address
itself (PC+36)
•
It will store the register R3 contents of memory location
M[PC+36]
•
It will left rotate the value of R3 36 times and will store the value in R3
A top-level view of computer function and interconnection
1. The processing required for a single instruction is called an
A. Instruction processing
B. Instruction cycle
C. Memory instruction
D. None of them
The right answer is
B) Instruction cycle
2. The fetched instruction is loaded into a register in the processor known as the
A. Memory
B. kernel
C. instruction register (IR)
D. memory registers
Right answer is
C) Instruction registers
3. The processor may perform some arithmetic or logic operation on data is
A. data processing
B. control
C. Processor
D. None of them
Right answer is
A) Data processing
4. The contents of the AC are stored in a location
A. 301
B. 302
C. 941
D. 303
Right answer is
C) 941
5. The collection of paths connecting the various modules is called
A. interconnections
B. communicating
C. joining
D. Interconnection structure
Right answer is
D) Interconnection structure
7. As with sequential access, direct access involves ——————— mechanism
A. Read
B. Write
C. None
D. Both a and b
Right answer is
D) both a and b
8. The mapping function is easily implemented using the
A. Registers
B. Memory
C. Main memory address
D. None of them
Right answer is
C) Main memory address
9. The problem with write-back is that portions of the main memory are
A. valid
B. invalid
C. access
D. None of them
Right answer is
B) Invalid
10. The——————— processor can be dynamically configured to support write-through caching.
A. Pentium 2
B. Pentium 3
C. Pentium 4
D. None of them
Right answer is
C) Pentium 4
11. The common form of read-mostly memory
A. EPROM
B. EEPROM
C. Flash memory
D. All of these
Right answer is
D) All of these
12. A more attractive form of read-mostly memory is
A. EPROM
B. EEPROM
C. Flash memory
D. None of them
Right answer is
B) EEPROM
13. A number of chips can be grouped together to form a
A. Main memory
B. Memory bank
C. Memory
D. None of them
Right answer is
B) Memory bank
14. EPROM stands for
A. Erasable programmable read-only memory
B. An electrically programmable read-only memory
C. Error programmable read-only memory
D. None of them
Right answer is
A) Erasable programmable read-only memory
15. SDRAM stands for
A. Static dynamic random access memory
B. System dynamic random access memory
C. Synchronous dynamic random access memory
D. Syndrome dynamic random access memory
Right answer is
C) Synchronous dynamic random access memory
16. There are typically hundreds of sectors per
A. Disk
B. Track
C. Gaps
D. Disk data
Right answer is
B) Track
18. The information can then be scanned at the same rate by rotating the disk at a fixed speed, known as
A. Constant angular velocity
B. Multiple zone recording
C. Disk data layout
D. None of them
Right answer is
A) Constant angular velocity
19. The ———————- byte is a special bit pattern that delimits the beginning of the field.
A. SYNCH
B. ID
C. 512
D. 600
Right answer is
A) SYNCH
20. A —————– disk can be removed and replaced with another disk
A. Nonremovable
B. Removable
C. Single Sided
D. Double Sided
Right answer is
B) Removable
21. The set of all the tracks in the same relative position on the platter is referred to as a
A. Platter
B. Tracks
C. Cylinder
D. None of them
Right answer is
C) Cylinder
22. An external device attaches to the computer by a link to an
A. Input module
B. Output module
C. Both a and b
D. None of them
Right answer is
C) Both a and b
22. Suitable for communicating with remote devices
A. Communication
B. Machine-readable
C. Human readable
D. None of them
Right answer is
A) Communication
23. In how many classify external devices
A. Communication
B. Machine-readable
C. Human readable
D. All of these
Right answer is
D) All of these
24. The user provides input through the
A. Microphone
B. keyboard
C. monitor
D. none of them
Right answer is
B) Keyboard
25. An I/O module is often responsible for error detection and for subsequently reporting errors to the
A. Processor
B. Main memory
C. RAM
D. None of them
Right answer is
A) processor
26. The most important system program is the
A. MAC
B. Operating system
C. Linux
D. None of them
Right answer is
B) Operating system
27. How many layers of a Computer System
A. One
B. Two
C. Three
D. Four
Right answer is
D) Four
28. The access function must provide protection of resources and data from ——————- users
A. Unauthorized
B. Authorized
C. End
D. None of them
Right answer is
a) Unauthorized
29. How many types of errors
A. Internal and external hardware errors
B. Memory errors
C. Device failure
D. All of these
Right answer is
D) All of these
30. Addition proceeds as if the two numbers were unsigned integers
A. Integers
B. Signed integers
C. Unsigned integers
D. None of them
Right answer is
C) Unsigned integers
31. Starting at any number on the circle, we can add positive k (or subtract negative k) to that number by moving k positions ————–
A. clockwise
B. anticlockwise
C. counterclockwise
D. none of them
Right answer is
a) clockwise
32. Compared with addition and subtraction, multiplication is a complex operation, whether performed in ——————————
A. software
B. hardware
C. both a and b
D. None of them
Right answer is
C) both a and b
33. Addition proceeds as if the two numbers were unsigned integers
A. Integers
B. Signed integers
C. Unsigned integers
D. None of them
Right answer is
C) Unsigned integers
34. Starting at any number on the circle, we can add positive k (or subtract negative k) to that number by moving k positions ————–
A. clockwise
B. anticlockwise
C. counterclockwise
D. none of them
Right answer is
A) clockwise
35. Compared with addition and subtraction, multiplication is a complex operation, whether performed in ——————————
A. software
B. hardware
C. both a and b
D. None of them
Right answer is
C) both a and b
36. We have seen that addition and subtraction can be performed on numbers in twos complement notation by treating them as
A. integers
B. signed integers
C. unsigned integers
D. none of them
Right answer is
C) unsigned integers
37. The division is somewhat more ———————– than multiplication
A. complex
B. easy
C. different
D. harder
Right answer is
A) complex
38. The operation is specified by a binary code, known as the
A. operation code or opcode
B. source operand reference
C. result operand reference
D. None of them
Right answer is
A) operation code or opcode
39. In most cases, the next instruction to be fetched immediately follows the
A. Back instruction
B. current instruction
C. next instruction
D. none of them
Right answer is
B) current instruction
40. During instruction execution, an instruction is read into an ——————– in the processor
A. Memory buffer register (MBR)
B. Address register (AD)
C. instruction register (IR)
D. index register (IR)
Right answer is
C) instruction register (IR)
41. These operations are performed primarily on data in
A. Random access memory
B. main memory
C. processor registers
D. none of them
Right answer is
C) processor registers
42. The various types of data upon which operations are performed is called
A. Data types
B. Operation repertoire
C. Instruction format
D. None of them
Right answer is
A) data type
43. We have seen that addition and subtraction can be performed on numbers in twos complement notation by treating them as
A. integers
B. signed integers
C. unsigned integers
D. none of them
Right answer is
C) unsigned integers
44. The division is somewhat more ———————– than multiplication
A. complex
B. easy
C. different
D. harder
Right answer is
A) complex
45. The most common addressing techniques
A. Stack
B. Direct
C. Indirect
D. All of these
Right answer is
D) All of these
46. Different opcodes will use different
A. addressing modes
B. mode fields
C. effective address
D. none of them
Right answer is
A) addressing modes
47. The disadvantage of the immediate addressing is that the size of the number is restricted to the size of the
A. Modes
B. Operand field
C. address field
D. registers
Right answer is
C) address field
48. The most common uses of displacement addressing
A. Relative addressing
B. Base-register addressing
C. Indexing
D. All of these
Right answer is
D) All of these
49. For this addressing method, indexing is not used.
A. Offset
B. Preindex
C. Postindex
D. None of them
Right answer is
A) Offset
50. The processor reads an instruction from memory (register, cache, main memory).
A. Fetch instruction
B. Fetch data
C. Process data
D. Interpret instruction
Right answer is
A) Fetch instruction
51. ———————— may be used only to hold data and cannot be employed in the calculation of an operand address.
A. Arithmetic register
B. Data registers
C. Index register
D. None of them
Right answer is
B) Data registers
52. Condition code bits are collected into one or more—————-
A. Registers
B. Address
C. Flags
D. Codes
Right answer is
A) registers
53. Contains a word of data to be written to memory or the word most recently read is
A. Program counter
B. Instruction register
C. Memory address register
D. Memory buffer register
Right answer is
D) memory buffer register
54. Interpret the opcode and perform the indicated operation.
A. Fetch
B. Execute
C. Interpret
D. None of them
Right answer is
B) Execute
55. These determine the functions to be performed by the processor and its interaction with memory.
A. Operation Performed
B. Operands used
C. Execution sequencing
D. None of them
Right answer is
A) operation performed
56. The use of a large set of registers should decrease the need to access
A. Operations
B. Memory
C. Register
D. None of them
Right answer is
B) memory
57. A —————– is defined to be the time it takes to fetch two operands from registers, perform an ALU operation, and store the result in a register.
A. Machine instruction
B. Machine cycle
C. Instruction register
D. Register operation
Right answer is
B) Machine cycle
58. The stages of the pipeline are an instruction—————— and an —————— that executes the instruction
A. fetch
B. execute/memory
C. both a and b
D. none of them
Right answer is
C) both a and b
59. For many years, the general trend in computer architecture and organization has been toward increasing processor complexity
A. Instruction
B. Addressing Modes
C. Specialized registers
D. All of these
Right answer is
D) All of these
-
An ________ is a program that takes basic computer instructions and converts them into a pattern of bits that the computer's processor can use to perform its basic operations.
- Assembler
- Debugger
- Editor
- Console
-
In which one of the following addressing modes, the operand does not specify an address but it is the actual data to be used.
- Direct
- Indirect
- Immediate
- Relative
-
In this figure, the constant value specified by the immediate field is added to the register value, and the resultant is the index of memory location that is referred i.e. Effective Address = A + (content of R) . Identify the addressing mode.- Displacement
- Immediate
- Indexed
- Relative
-
In ________ address mode, the actual data is stored in the instruction.
- Direct
- Indirect
- Immediate
- Relative
-
Which one of the following registers store a previously calculated value or a value loaded from the main memory?
- Accumulator
- Address Mask
- Instruction Register
- Program Counter
-
Which field of the machine language instruction is the “type of operation” that is to be performed?
- Op-code
- CPU registers
- Memory cells
- I/O locations
-
An instruction that specifies one operand in memory and one operand in a register would be known as a ________ address instruction.
- 2-1/2
- 1-1/2
- 0
- 2
-
Which one of the following instructions is used to load register from memory using a relative address?
- la
- lar
- ldr
- str
-
Which one of the following is an address (binary bit pattern) issued by CPU?
- Memory
- Effective
- Base
- Nex t instruction
-
The instruction ________ will load the register R3 with the contenets of the m\emory location M [PC+56]
- Add R3, 56
- lar R3, 56
- ldr R3, 56
- str R3, 56
-
Which instruction is used to store register to memory using relative address?
- ld instruction
- ldr instruction
- lar instruction
- str instruction
-
Type A of SRC has which of the following instructions?
- andi, instruction
- No operation or nop instruction
- lar instruction
- ldr instruction
- Stop operation or stop instruction
- 1 & 2
- 2 & 3
- 3 & 5
- 2 & 5
-
Which one of the following languages presents a simple, human-oriented language to specify the operations, register communication and timing of the steps that take place within a CPU to carry out higher level (user programmable) instructions?
- Assembly Language
- OOP(Object Oriented Language)
- RTL (Register Transfer Language)
- UML(Unified Modeling language)
-
What does the RTL expression [M(1234)] means?
- The contents of memory whose address is 1234.
- The contents of data register 1234
- The effective address of register 1234
- The address of memory whose address is 1234.
-
Which one of the following is a binary cell capable of storing one bit of information?
- Decoder
- Flip-flop
- Multiplexer
- Diplexer
-
Which one of the following is a bi-stable device, capable of storing one bit of information?
- Decoder
- Flip-Flop
- Multiplexer
- Diplexer
-
Which type of instructions load data from memory into registers, or store data from registers into memory and transfer data between different kinds of special-purpose registers?
- Arithmetic
- Control
- Data transfer
- Floating point
-
Which one of the following portions of an instruction represents the operation to be performed?
- Address
- Instruction code
- Opcode
- Operand
-
Which type of instructions enables mathematical computations?
- Arithmetic
- Control
- Data transfer
- None of the given
-
Which one of the following is the memory organization of EAGLE processor?
- 8-bits
- 16-bits
- 32-bits
- 64-bits
-
Which type of instructions help in changing the flow of the program as and when required?
- Arithmetic
- Control
- Data transfer
- Floating point
-
What is the instruction length of the FALCON-E processor?
- 8 bits
- 16 bits
- 32 bits
- 64 bits
-
What is the instruction length of the FALCON-A processor?
- 8-bits
- 16-bits
- 32-bits
- 64-bits
-
What is the instruction length of the SRC and Falcon E processor?
- 8 bits
- 16 bits
- 32 bits
- 64 bits
-
Which one of the following registers holds the address of the next instruction to be executed?
- Accumulator
- Address Mask
- Instruction Register
- Program Counter
-
FALCON-A processor bus has 16 lines or is 16-bits wide while that of SRC ________ wide.
- 8-bits
- 16-bits
- 32-bits
- 64-bits
-
For any of the instructions that are a part of the instruction set of the SRC, there are certain _________required which may be used to select the appropriate function for the ALU to be performed, to select the appropriate registers, or the appropriate memory location.
- Register
- Control signals
- Memory
- None of the given
-
________ control signal enable the input to the PC for receiving a value that is currently on the internal processor bus.
- LPC
- INC4
- LC
- I
-
________ operation is required to change the processor’s state to a known, defined value.
- Change
- Reset
- Update
- None of the given
-
When is the “Divide error interrupt" generated?
- When an attempt is made to divide by decimal number
- When an attempt is made to multiply by zero
- When an attempt is made to divide by zero
- When negative number is stored in a register
-
What should be the behavior of interrupts during critical sections?
- Must remain disable
- Must remain Enable
- Can be either enable or disable
- only important interrupts be enable
-
A user program has to delete a file. The user program will be executing in the user mode. When it makes the specific system call to delete the file, an interrupt will be generated, this will cause the processor to halt its current activity and switch to supervisor mode. Once in supervisor mode, the operating system will delete the file and then control will return to the user program. This is an example of
- Hardware interrupt
- Software interrupt
- Exception
- All of the given
-
________ is/a re defined as the number of instructions processed per second.
- Throughput
- Latency Time to process 1 request.
- Throughput and Latency
- None of the given
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